description the encoder ic consists of 13 signal photo diode channels and 1 monitor photo diode channel and is used for the optical reading of rotary carriers (i.e., discs). the photodiodes are accompanied with precision amplifiers plus additional circuitry. the monitor channel is used to drive a constant current source for the highly collimated ir illumination system. functional description background the 13 signal channels are set up as: 1. two precision defining signals (a0, a09), which are two 90 electrical shifted sine, cosine signals. these signals are conditioned to be compensated for offset and gain errors. after conditioning they are on chip interpolated 2. 11 analog (a1-a11) channels which are directly digitized by precision comparators with hysterisis tracking. the digitized signals are called d1-d11. an internal correction and synchronization module allows the composition of a true 16 bit gray code by merging the data bits of (1) and (2) by still keeping the code monotonic. there is a gray code correction feature for this encoder. this gray code correction can be disabled/enabled by the pin korr. the gain and offset conditioning value of the sine and cosine signals are preloaded on-chip by factory. this will compensate for mechanical sensor misalignment error. aeas-7000 ultra-precision 16 bit gray code absolute encoder module data sheet features ? minimum mechanical alignment during installation ? two sine/cosine true differential outputs with 1024 periods for unit alignment ? integrated highly collimated illumination system ? 11 digital tracks plus 2 sin/cos tracks generate precise 16 bit gray code ? ultra fast, 1 s cycle for serial data output word equals 16 mhz ? on-chip interpolation and code correction ? msb can be inverted for changing the counting direction ? internally built-in monitor track for tracking the light level of the led. ? watch dog with alarm output ? C25c to +85c operating temperature applications ? rotary application up to 16 bit/360 absolute position ? linear positioning system ? cost effective solution for direct integration into oem systems
2 signal-channels a1-a11 the photocurrent of the photo diodes is fed into a trans-impedance amplifier. the analog output of the amplifier has a voltage swing of (dark/light) about 1.3 v. every output is transformed by precision comparators into digital signals (d1-d11). the threshold is at vdd/2 (=analog-reference), regulated by the monitor channel. monitor channel with led control at pins ledr and lerr the analog output signal of the monitor channel is regulated by the led current. an internal bipolar transistor sets this level to vdd/2 (control voltage at pin ledr). thus the signal swing of each output is symmetrical to vdd/2 (=analog-reference) the error bit at pin lerr is triggered if the ve of the internal bipolar transistor is larger than vdd/2. signals channels a0, a09 with signal conditioning and calibration these two channels give out a sine and cosine wave, which are 90 degree phase shifted. these signals have amplitudes which are almost constant due to the led current monitoring. due to amplifier mismatch and mechanical misalignment, the signals have gain and offset errors. these errors are eliminated by an adaptive signal conditioning circuitry. the conditioning values are on-chip preprogrammed by factory. the analog output signals of a0 and a09 are supplied as true- differential voltage with a peak to peak value of 2.0 v at the pins a09p, a09n, a0p, a0n. interpolator for channels a0,a09 the interpolator generates the digital signals d0,d09 and d-1 to d-4. the interpolated signals d-1 to d-4 extend the 12 bit gray code of the signals d11.d0 to form a 16 bit gray code. d0 and d09 are digitized from a0 and a09. the channels a0-a11 and a09 have very high dynamic bandwidth, which allows a real time monotone 12 bit gray code at 12000 rpm. the interpolated 16 bit gray code can be used up to 1000 rpm only. at more than 1000 rpm, only the 12 bit gray code from the msb side can be used. lsb gray code correction (pin korr) this function block synchronizes the switching points for the 11 bit gray code of the digital signals d1 to d11 with d0 and d09 (digitized signal of a0 and a09). this gray code correction only works for the 12 bit msb(4096 steps per revolution). the correction is not for the 4 excess interpolated bits of the 16 bit gray code. gray code correction can be switched on or off by putting the pin korr =1(on) or =0(off). msbinv and dout pins the serial interface consists of a shift register. the most significant bit, msb (d11) will always be sent first to dout. the msb can be inverted (change code direction) by using pin msbinv. din and nsl pins the serial input din allows the configuration as ring register for multiple transmissions or for cascading 2 or more encoders. din is the input of the shift register that shifts the data to dout. the nsl pin controls the shift register, to switch it between load (1) or shift (0) mode. under load mode, dout will give the logic of the msb, i.e., d11. under shift mode (0), coupled with the scl, the register will be clocked, and gives out the serial word output bit by bit. as the clock frequency can be up to 16 mhz, the transmission of the full 16 bit word can be done within 1s. valid data of dout should be read when the scl clock is low. please refer to timing diagram (figure 3).
3 package dimensions device selection guide 1 figure 1. package dimensions notes: 1. for other options of absolute encoder module, please refer to factory. notes: 1. 3rd angle projection 2. dimensions are in millimeters 3. unless otherwise specified, the tolerances are: xx. C 0.3; xx.x C 0.1; xx.xx C 0.03 4. codewheel and readhead mounting tolerances for radial, tangential and z gap are: radial : 50 m tangential : 40 m z gap : 50 m (z gap between code disk and reticle) code disk ? 42.1 ? 8.0 h6 22.6 18.850.2 1.2 0.1 2x11 -1.27mm pitch header 3.65 0.35 +0.05 - 0.10 35.1 24.1 21.2 9.2 8.5 10 24.0 12.0 ? 3.2(2x) ? 56 readhead z + z - radial + tangential+ c l m1.6 tap 5dp (2x) part number resolution operating temperature (c) output output code dc supply voltage (v) AEAS-7000-1GSD0 13 bit -25 to 85 serial gray code +4.5 to +5.5 aeas-7000-1gsg0 16 bit -25 to 85 serial gray code +4.5 to +5.5
4 absolute maximum ratings 1, 2 recommended operating condition notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress r ating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of th is specification is not implied. 2. exposure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. voltage ripple of supply voltage, vripple, should be within 100mvpp or less for improved accuracy. parameter symbol limits units dc supply voltage vd -0.3 to + 6.0 v input voltage v in -0.3 to +vd +0.3 v output voltage v out -0.3 to +vd +0.3 v relative air humidity (non-condensing) rh 85 % operating temperature t a - 25 to +85 c storage temperature t s - 35 to +85 c parameter symbol values units notes min. typ. max. dc supply voltage vd + 4.5 + 5.0 +5.5 v 1 operating temperature t a - 25 25 +85 c input high level v ih 0.7*vd vd v input low level v lh 00.3*vdv electrical characteristics electrical characteristics over recommended operating range, typical at ta=25 c and vd = 5v notes: 1. lsb accuracy will also depend on mechanical precision of the shaft, bearings, hub etc. final accuracy of the encoder module is dependent on the precision of the total assembly. 2. accuracy would be influenced by installation control and the bearing and shaft type being used. 3. other test conditions to determine accuracy are briefly listed as follows: (a) at nominal radial, tangential and gap position (b) on dual preloaded bearing with absolute assembly total runout of not exceeding 0.01 mm tir (c) both vdd & vdda rc filters placed not more than 20mm from header pins parameter symbol condition values units min typical max total operating current i total 25 ma digital input-pull down current i pd -20 -5 a digital input-pull up current i pu 30 160 a digital ouput-h-level v oh i oh = 2 ma vd -0.5 v vd v digital ouput-l-level v ol i ol = - 2 ma 0 0.5 v scl clock frequency f scl 16 mhz duty cycle scl clock t lh t lh = h/(l+h) 0.4 0.6 accuracy within one revolution 1, 2, 3 f scl = 5mhz rpm =80 v ripple <50mvpp 2 bit signal frequency of a0, a09 f a0 , f a09 250 khz
5 no. pin name description function notes1 1 nc do not use. internally connected to cathode of led 2 korr digital-input 1 = gray code correction active cmos, internal pu 3 probe_on digital-input do not use cmos, internal pd 4 pcl digital input positive edge do not use cmos, internal pu 5 stcal digital input positive edge negative edge do not use unnecessarily cmos, internal pd 6 msbinv digital-input 1 = most significant bit, msb, inverted cmos, internal pd 7 din digital input shift register input. use for cascading only. cmos, internal pd 8 nsl digital-input shift-register shift (=0) / load(=1) control cmos, internal pu 9 scl digital-input positive edge shift-register clock cmos, internal pu 10 dout digital output shift-register data out (msb first) cmoss, 2ma 11 do digital output do signal cmos, 2ma 12 dprobe digital output do9 signal cmos, 2ma 13 vdd supply voltage +5v supply digital 14 gnd ground for supply voltage gnd for 5v supply analog/digital 15 a09p analog output a09 positive(+true diff.) cmos, analog out 16 gnd ground for supply voltage gnd for 5v supply analog/digital 17 a0p analog output a0 positive(+true diff.) cmos, analog out 18 a09n analog output a09 negative(-true diff.) cmos, analog out 19 vdda supply voltage +5v supply analog 20 a0n analog output a0 negative (- true dif) cmos, analog out 21 lerr digital output ir-led current limit signal cmos, 2ma 22 ledr analog output do not use cmos, analog out pin description figure 2. pinout configuration notes: 1. internal pu/pd = internal pull-up (typ. 50 a)/ pull-down (typ. 10 a) cmos-transistor-rs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 esd warning: handling precautions should be taken to avoid static discharge.
6 figure 3. timing diagram figure 4. schematic for using aeas-7000 analog outputs msbinv pcl probe_on korr lerr lerr d0 10r min 100 tantal 0r to 2r tantal min 22 vdd vdd (c's optional) din nsl scl dout gnd vcc gnd vcc(+5v) application - logic korr probe_on a09n_aref gnd vdda a0p_a0 a0n_mon a09p_apr ledr pcl msbinv dout scl din nsl vdd dprobe d0 d09 configuration and probe control stcal stcal korr is for gray code correction for 12 bits resolution only. msbinv is for user to change between counting up and counting down for a given rotating direction. msb(d11) will always be sent out to dout first. ledr, do not connect to this pin. lerr will be high when the light output perceived by the photo diode array is low, and the led current is under overdrive mode. this is an indicator when light intensity is at a critical stage affecting the performance of the encoder. it is caused by contamination of the codewheel or led degradation. using the aeas-7000 important note: the rc-filter combination, especially on vdda, is used to filter spikes and transients and is strongly recommended. it is advised that the tantalum caps be put as close to the vdd and vdda pins as possible. it is recommended to ground the probe_on pin during normal operation. leave pcl unconnected. a09n and a0n are the negative cosine and sine waves, the negative versions of a09p and a0p. d0 is used to check the d0 signal. d0 is the digitized signal of a0. dprobe is used to check d09, the digitized signal of a09. recommended to be used for testing purpose only. nsl scl 1 2 14 15 16 lapse time between words, set by nsl 1 frame = 16 bits note: valid data is when nsl is low d11 d10 d-3 d-4 d11 dout (serial)
7 ?12 0.8 depth as adhesive reservoir 58 ?16 ?15 ?11 20 0.01 a 0.02 0.01 a 0.02 ?0.01 12 4.2 0.01 a ?18 ?10h6 1 ?8.02h6 2 +0.03 -0 +0 - 0.01 +0 - 0.01 ( ) ( ) motor end is user specified straightness flatness perpendicularity total run-out figure 5. design reference for code disk hub- shaft operation 1. after powering up the unit using v d =+5 v and connecting gnd to ground, trigger input pins nsl and scl using the timing diagram (figure 3). nsl is a control pin for the internal shift register. nsl=1 is load mode while nsl=0 is shift mode for the shift register. when nsl=0 and combined with clock pulses, the serial gray code will be shifted out to dout bit by bit per every clock pulse. valid data of dout should be sampled at the falling edges of the clock pulses. 2. the 16 bit serial gray code can be tapped out from the pin dout, most significant bit (d11) first. the rate of the 16 bit gray code serial transfer rate is dependent on the scl clock frequency. the faster the clock, the faster the transfer rate. the maximum clock rate the aeas-7000 can take is 16 mhz, which means the entire 16 bit gray code can be serially transferred out in 1 s. 3. whenever nsl is high, the dout will have the logic of the msb (d11). after nsl goes low, the number of bits being transferred out will depend on the number of clock pulses given to scl. the default is 16 bit clock pulses for the 16 bit gray code. if for other application where another number other than 16 is needed, just supply the corresponding number of clock pulses to the scl, e.g., 12 bit, 13 bit, 14 bit or 15 bit, and the corresponding length of gray code words with the corresponding resolution can be obtained. plug & play hub-shaft design figure 5 details the hub-shaft design of which the dimensions must be strictly followed for the plug & play feature of the aeas-7000 to work. in order to secure the code disk to the hub, an adhesive should be utilised. it is recommended to use delo-duopox, 1895 from delo or its equivalence. stainless steel is recommended as the hub-shaft material. a more detailed instruction for aeas-7000 installation consideration can be found in aeas-7000 application note.
aea legend 1 = 5v g = gray code s = serial output mode - 7000 - 1 g s s - standard (-25?c to +85?c) 0 d - 13 bits g - 16 bits ordering information AEAS-7000-1GSD0 single-turn, -25 to +85c, detached encoder set, 5v, serial, 13 bit aeas-7000-1gsg0 single-turn, -25 to +85c, detached encoder set, 5v, serial, 16 bit heds-8933 m echanical alignment tool for aeas-7000 note: for alignment process, please refer to avago technologies website (www.avagotech.com) for application note or contact factory. for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, limited in the united states and other countrie s. data subject to change. copyright ? 2006 avago technologies pte. all rights reserved. obsoletes 5988-9627en 5989-4140en - may 29, 2006
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